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description the cxp87452/87460 is a cmos 8-bit micro- computer which consists of a/d converter, serial interface (2ch independently), timer/counter, time base timer, vector interruption, high precision timing pattern generation circuit (ppg 2ch independently, rtg 2ch independently), pwm generator, general purpose prescaler, pwm for tuner, vcr vertical sync separation circuit and the measuring circuit which measure signals of capstan fg and drum fg/pg and other servo systems, as well as basic configurations like 8-bit cpu, rom, ram and i/o port. they are integrated into a single chip. also cxp87452/87460 provides power on reset function, sleep/stop function which enables to lower power consumption . features a wide instruction set (213 instructions) which cover various types of data ?16-bit arithmetic instruction/multiplication and division instructions/boolean bit operation instruction minimum instruction cycle during operation 333ns/12mhz (3.0 to 5.5v) during operation 250ns/16mhz (4.5 to 5.5v) incorporated rom capacity 52k bytes (cxp87452) 60k bytes (cxp87460) incorporated ram capacity 1568 bytes peripheral functions ?a/d converter 8-bit, 12-channel, successive approximation system (conversion time: 20s/16mhz) ?serial interface incorporated buffer ram (1 to 32 bytes auto transfer) 1-channel incorporated 8-bit and 8-stage fifo (1 to 8 bytes auto transfer) 1-channel ?timer 8-bit timer, 8-bit timer/counter, 19-bit time base timer ?high precision timing pattern generator ppg 19 pins 32-stage programmable ppg 10 pins 21-stage programmable rtg 5 pins 2-channel ?pwm/da gate output pwm 12-bit, 2-channel (repetitive frequency 62.5khz/16mhz) da gate pulse 12-bit, 4-channel ?servo input control capstan fg, drum fg/pg, ctl input ?vsync separator ?frc capture unit incorporated 26-bit and 8-stage fifo ?pwm output 14-bit, 1-channel ?general purpose prescaler 10-bit (system clock asynchronous) ?pulse cycle measurement circuit interruption 18 factors, 14 vectors, multi-interruption possible standby mode sleep/stop package 100-pin plastic qfp/lqfp piggyback/evaluation chip cxp87400 100-pin ceramic qfp/lqfp structure silicon gate cmos ic ?1 cxp87452/87460 e95111-ps cmos 8-bit single chip microcomputer sony reserves the right to change products and specifications without prior notice. this information does not convey any license by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustrating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. 100 pin qfp (piastic) 100 pin lqfp (piastic)
?2 cxp87452/87460 a/d converter serial interface unit (ch0) buffer ram interrupt controller spc700 cpu core rom 52k/60k bytes prescaler/ time base timer ram 1568 bytes clock generator/ system control 12 an0 to an3 si0 cs0 pi7/si1 sck0 av dd pe1/int2 extal xtal rst v dd vss port c 8 pc0 to pc7 port d 8 pd0 to pd7 port i pi1 to pi7 port j 8 pj0 to pj7 port g 8 pg0 to pg7 port h 8 ph0 to ph7 port a 8 pa0 to pa7 port e 2 6 pe0 to pe1 pe2 to pe7 realtime pulse generator 2 pf0/an4 to pf7/an11 2 pe0/int0 frc capture unit fifo ram ch0 ch1 19 5 2 port b 8 pb0 to pb7 port f pf0 to pf3 4 4 pf4 to pf7 av ref avss mp pi4/int1 port k 1 pk0 programmable pattern generator (ch1) ram 10 2 3 2 4 4 2 2 serial interface unit (ch1) fifo 8bit timer/counter 0 8bit timer 1 v sync separator capstan drum ctl servo input control programmable prescaler 14bit pwm generator 12bit pwm generator ch0 12bit pwm generator ch1 pulse measure unit so0 pi6/so1 pi5/sck1 pe1/ec pi3/to pg4/sync0 pg5/sync1 pg6/exi0 pg7/exi1 pg0/cfg pg1/dfg pg2/dpg pg3/pbctl pi0/pck/osci pk0/osco pi1/po pe0/xout pe2/pwm0 pe4/daa0 pe6/dab0 pe3/pwm1 pe5/daa1 pe7/dab1 pg4/pmi pg7/pmsk pi2/pwm 1 7 pi0 ppo100 to ppo113 ppo107 ppo112 rto7 rto3 ppo000 to ppo018 19 10 programmable pattern generator (ch0) to to block diagram
?3 cxp87452/87460 a a pi6/so1 pi7/si1 pe0/int0/xout pe1/ec/int2 pe2/pwm0 pe3/pwm1 pe4/daa0 pe5/daa1 pe6/dab0 pe7/dab1 pg0/cfg pg1/dfg pf2/dpg pg3/pbctl pg4/sync0/pmi pg5/sync1 pg6/exi0 pg7/exi1/pmsk an0 an1 an2 an3 pf0/an4 pf1/an5 pf2/an6 pf3/an7 av dd av ref av ss pf4/an8 pb5/ppo013/ppo113 pb4/ppo012/ppo112 pb3/ppo011 pb2/ppo010 pb1/ppo009 pb0/ppo008 pc7/rto7 pc6/rto6 pc5/rto5 pc4/rto4 pc3/rto3 pc2/ppo018 pc1/ppo017 pc0/ppo016 pj7 pj6 pj5 pj4 pj3 pj2 pj1 pj0 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 pb6/ppo014 pb7/ppo015 pa0/ppo000/ppo100 pa1/ppo001/ppo101 pa2/ppo002/ppo102 pa3/ppo003/ppo103 pa4/ppo004/ppo104 pa5/ppo005/ppo105 pa6/ppo006/ppo106 pa7/ppo007/ppo107 nc v dd v ss pk0/osco pi0/pck/osci pi1/po pi2/pwm pi3/to pi4/int1 pi5/sck1 ph7 ph6 ph5 ph4 ph3 ph2 ph1 ph0 mp rst v ss xtal extal cs0 si0 so0 sck0 pf7/an11 pf6/an10 pf5/an9 mask option 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 40 39 38 37 36 35 34 31 32 33 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 70 69 68 67 63 64 65 66 61 62 71 72 73 74 81 82 83 84 75 76 77 78 88 87 86 85 79 80 89 90 10 0 99 98 97 96 95 94 91 92 93 1 pin configuration 1 (top view) 100 pin qfp package note) 1. nc (pin 90) is always connected to v dd . 2. vss (pins 41 and 88) are both connected to gnd.
?4 cxp87452/87460 pin configuration 2 (top view) 100 pin lqfp package aa aa pi6/so1 pi7/si1 pe0/int0/xout pe1/ec/int2 pe2/pwm0 pe3/pwm1 pe4/daa0 pe5/daa1 pe6/dab0 pe7/dab1 pg0/cfg pg1/dfg pf2/dpg pg3/pbctl pg4/sync0/pmi pg5/sync1 pg6/exi0 pg7/exi1/pmsk an0 an1 an2 an3 pf0/an4 pf1/an5 pf2/an6 pb3/ppo011 pb2/ppo010 pb1/ppo009 pb0/ppo008 pc7/rto7 pc6/rto6 pc5/rto5 pc4/rto4 pc3/rto3 pc2/ppo018 pc1/ppo017 pc0/ppo016 pj7 pj6 pj5 pj4 pj3 pj2 pj1 pj0 pd7 pd6 pd5 pb6/ppo014 pb7/ppo015 pa0/ppo000/ppo100 pa1/ppo001/ppo101 pa2/ppo002/ppo102 pa3/ppo003/ppo103 pa4/ppo004/ppo104 pa5/ppo005/ppo005 pa6/ppo006/ppo106 pa7/ppo007/ppo107 nc v dd v ss pk0/osco pi0/pcl/osci pi1/po pi2/pwm pi3/to pi4/int1 pi5/sck1 ph2 ph1 ph0 mp rst v ss xtal extal cs0 si0 so0 sck0 pf7/an11 pf6/an10 pf5/an9 mask option ph7 ph6 ph5 ph4 ph3 pd4 pd3 pd2 pd1 pd0 pf4/an8 av ss pf3/an7 av dd av ref pb4/ppo012/ppo112 pb5/ppo013/ppo113 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 40 39 38 37 36 35 34 31 32 33 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 60 70 69 68 67 63 64 65 66 61 62 71 72 73 74 81 82 83 84 75 76 77 78 88 87 86 85 79 80 89 90 10 0 99 98 97 96 95 94 91 92 93 1 59 note) 1. nc (pin 88) is always connected to v dd . 2. vss (pins 39 and 86) are both connected to gnd.
?5 cxp87452/87460 output/ real time output output/ real time output i/o/ real time output i/o/ real time output i/o input/input/output input/input/input output/output output/output output/output output/output output/output output/output input input/input output/input i/o ouput input input (port a) 8-bit output port. data is gated with ppo0 and ppo1 contents by or-gate and they are output. (8 pins) (port b) 8-bit output port. data is gated with ppo0 and ppo1 contents by or-gate and they are output. (8 pins) (port c) 8-bit i/o port. enables to specify i/o by bit unit. data is gated with ppo or rto contents by or-gate and they are output. (8 pins) (port d) 8-bit i/o port. enable to specify i/o by 4-bit unit. enables to drive 12ma sinc current. (during 5v 0.5v operation) (8 pins) (port e) 8-bit port. lower 2 bits are input port and upper 6 bits are output port. (8 pins) analog input pins to a/d converter. (12 pins) (port f) lower 4 bits are input port and upper 4 bits are output port. lower 4 bits also serve as standby release input pin. (8 pins) serial clock (ch0) i/o pin. serial data (ch0) output pin. serial data (ch0) input pin. serial chip select (ch0) input pin. external event input pin for timer/counter. input pin to request external interruption. active when falling edge. input pin to request external interruption. active when falling edge. 1/2 dividing clock output of xtal or osco. pwm output pins. (2 pins) da gate pulse output pins. (4 pins) programmable pattern generator (ppg0, ppg1) output. functions as high precision real time pulse output port. ( ppg0 19 pins ) ppg1 10 pins real time pulse generator (rtg) output. functions as high precision real time pulse output port. (5 pins) symbol i/o description pa0/ppo000 /ppo100 to pa7/ppo007 /ppo107 pb0/ppo008 to pb7/ppo015 pc0/ppo016 to pc2/ppo018 pc3/rto3 to pc7/rto7 pd0 to pd7 pe0/int0 /xout pe1/ec/int2 pe2/pwm0 pe3/pwm1 pe4/daa0 pe5/daa1 pe6/dab0 pe7/dab1 an0 to an3 pf0/an4 to pf3/an7 pf4/an8 to pf7/an11 sck0 so0 si0 cs0 pin description
?6 cxp87452/87460 pg0/cfg pg1/dfg pg2/dpg pg3/pbctl pg4/sync0 /pmi pg5/sync1 pg6/exi0 pg7/exi1/ pmsk ph0 to ph7 pi0/pck /osci pi1/po pi2/pwm pi3/to pi4/int1 pi5/sck1 pi6/so1 pi7/si1 pj0 to pj7 input/input input/input input/input input/input input/input/input input/input input/input input/input/input output input/input/input i/o/output i/o/output i/o/output i/o/input i/o/i/o i/o/output i/o/input i/o capstan fg input pin. drum fg input pin. drum pg input pin. playback ctl pulse input pin. composite sync signal input pin. measuring pulse signal input pin of pulse cycle measuring unit. measuring enable signal input pin of pulse cycle measuring unit. (port g) 8-bit input port. (8 pins) (port h) 8-bit output port; large current, n-ch open drain output. (8 pins) external clock input pin of general purpose prescaler. general purpose prescaler output pin. 14-bit pwm output pin. timer/counter, output pin. (duty = 50%) input pin to request external interruption. active when falling edge. serial clock (ch1) i/o pin. serial data (ch1) output pin. serial data (ch1) input pin. (port i) lower 1 bit is input port (mask option) and upper 7 bits are i/o port. i/o port can be specified by bit unit. (8 pins) symbol i/o description external input pin to frc capture unit. connecting pin of crystal oscillation circuit for general purpose prescaler. (mask option) (port j) 8-bit i/o port. function as standby release input can be specified by bit unit. i/o can be specified by bit unit.
?7 cxp87452/87460 pk0/osco rst mp av dd av ref av ss v dd v ss input/output i/o input input connecting pin of crystal oscillator for system clock. when supplying the external clock, input the external clock to extal pin and input opposite phase clock to xtal pin. input port. (mask option) system reset pin of active "l" level. rst pin is i/o pin, which output "l" level by incorporated power on reset function when power on. (mask option) microprocessor mode input pin. always connect to gnd. positive power supply pin of a/d converter. reference voltage input pin of a/d converter. gnd pin of a/d converter. positive power supply pin. gnd pin. connect both vss pins to gnd. connecting pin of crystal oscillation circuit for general purpose prescaler. (mask opiton) xtal extal output input symbol i/o description
?8 cxp87452/87460 ppo, rto data data bus rd (port c) aaaa aa port c direction aaaa aaaa port c data input protection circuit ip (every bit) aa aa data bus rd (port d) aaaa aaaa aa aa port d direction aaaa aaaa port d data large current 12ma ip (every 4 bits) aa aa pd0 to 3 pd4 to 7 aaaa aaaa aa aa ppo0 data ppo1 data data bus output becomes active from high impedance by data writing to port register. port a or port b rd pin when reset circuit format port a port b port b port c port d hi-z hi-z hi-z hi-z pa0/ppo000 /ppo100 to pa7/ppo007 /ppo107 pb4/ppo012 /ppo112 to pb5/ppo013 /ppo113 10 pins pb0/ppo008 to pb3/ppo011 pb6/ppo014 to pb7/ppo015 6 pins pc0/ppo016 to pc2/ppo018 pc3/rto3 to pc7/rto7 8 pins pd0 to pd7 8 pins aaaa aaaa aa aa ppo0 data data bus output becomes active from high impedance by data writing to port register. port a or port b rd input/output circuit format for pins
?9 cxp87452/87460 data bus rd (port e) a aa a aaaa aa aa aaa a a a a a a aaa da gate output or pwm output hi-z control mpx aaaa aaaa port e data port e function select register data bus rd (port e) aaa aaa aa aa aa aa aa aa da gate output hi-z control mpx aaa aaa port e data port e function select register data bus rd (port e) aaa aaa aa aa port e function select register ip aa aa aa aa aa aa aa 1/2 ps1 osco to interruption circuit mpx aa aa aa aa ip rd (port e) data bus schmitt input port e port e port e port e hi-z hi-z hi-z h level pe1/ec/int2 1 pin pe0/int0 /xout 1 pin pe2/pwm0 pe3/pwm1 pe4/daa0 pe5/daa1 4 pins pe6/dab0 pe7/dab1 2 pins pin when reset circuit format
?10 cxp87452/87460 data bus rd (port f) aaaa aaaa aa port/ad select ip aa aa aaaa aaaa port f data a/d converter input multiplexer aa aa aa ip rd (port g) data bus schmitt input pulse cycle measurement unit input servo input note) for pg4/sync0, pg5/sync1, cmos schmitt input and ttl schmitt input can be selected with the mask option. data bus rd (port h) aa aa aaa aaa port h data large current 12ma rd (port f) data bus aa aa aa aa ip input multiplexer a/d converter port f port f port g hi-z hi-z hi-z hi-z an0 to an3 4 pins pf0/an4 to pf3/an7 4 pins pf4/an8 to pf7/an11 4 pins pg0/cfg pg1/dfg pg2/dpg pg3/pbctl pg4/sync0/pmi pg5/sync1 pg6/exi0 pg7/exi1/pmsk 8 pins port h hi-z ph0 to ph7 8 pins aa aa aa aa ip a/d converter input multiplexer pin when reset circuit format
?11 cxp87452/87460 a a aa aa aa pi1: from general purpose prescaler pi2: from 14-bit pwm pi3: from timer/counter mpx aaa aaa port i data aa aa ip data bus rd (port i) aaa aaa port i direction aaaa aaaa port i function select aa aa pi4: to interruption circuit pi7: to serial ch1 aaaa aaaa port i data a a ip data bus rd (port i) aaaa aaaa port i direction schmitt input aa aa aaa a a a aaa mpx aaaa aaaa port i data aa aa ip data bus rd (port i) aaaa aaaa port i direction aaaa aaaa port i function select aa aa aa aa mpx to serial ch1 from serial ch1 note) pi5 is schmitt input pi6 is inverter input aa aa standby release aaa aaa port j data aa aa ip data bus rd (port j) aaa aaa port j direction a a edge detection port i port i port i port j hi-z hi-z hi-z hi-z pi1/po pi2/pwm pi3/to 3 pins pi4/int1 pi7/si1 2 pins pi5/sck1 pi6/so1 2 pins pj0 to pj7 8 pins pin when reset circuit format
?12 cxp87452/87460 aa aa aa aa ip schmitt input to sio so0 output enable aa aa so0 from sio aa aa aa ip schmitt input pull-up resistor from power on reset circuit (mask option) mask option op aa aa a a ip cpu mode aa aa a a ip aa aa osci osco fig. 1 aa aa aa ip fig. 2 data bus pi0/pck or pk0 note) circuit format of fig. 1 or fig. 2 can be selected with mask option. rd port i port k cs0 si0 2 pins hi-z so0 2 pins rst 1 pin l level mp 1 pin hi-z port i port k oscillation hi-z pi0/pck/osci pk0/osco 2 pins sck0 output enable aa aa internal serial clock from sio aa aa ip schmitt input external serial clock to sio aa aa aa aa ip aa aa extal xtal ?shows the circuit composition during oscillation. ?feedback resistor is removed during stop. 1 pin hi-z sck0 1 pin hi-z extal xtal oscillation pin when reset circuit format
?13 cxp87452/87460 * 1 av dd and v dd should be set to a same voltage. * 2 v in and v out should not exceed v dd + 0.3v. (cs0, si0, pg and ph excluded.) * 3 the large current operation transistors are the n-ch transistors of the pd and ph ports. note) usage exceeding absolute maximum ratings may permanently impair the lsi. normal operation should better take place under the recommended operating conditions. exceeding those conditions may adversely affect the reliability of the lsi. power supply voltage input voltage output voltage high level output current high level total output current low level total output current operating temperature storage temperature allowable power dissipation v dd av dd av ss v in v out i oh i oh i ol i olc i ol topr tstg p d low level output current ?.3 to +7.0 avss to +7.0 * 1 ?.3 to +0.3 ?.3 to +7.0 * 2 ?.3 to +7.0 * 2 ? ?0 15 20 130 ?0 to +75 ?5 to +150 600 380 v v v v v ma ma ma ma ma ? ? mw total of output pins other than large current output pins: per pin large current output pin * 3 : per pin total of output pins qfp lqfp item symbol rating unit remarks absolute maximum ratings (vss = 0v)
?14 cxp87452/87460 analog power supply high level input voltage low level input voltage operating temperature power supply voltage 5.5 5.5 5.5 5.5 v dd v dd 5.5 5.5 v dd + 0.3 v dd + 0.2 0.3v dd 0.2v dd 0.2v dd 0.8 0.4 0.2 +75 v v v v v v v v v v v v v v v v ? item symbol min. max. unit remarks 3.0 2.7 2.5 3.0 0.7v dd 0.8v dd 2.2 v dd ?0.4 v dd ?0.2 0 0 0 ?.3 ?.3 ?0 av dd v ih v ihs v ihts v ihex v il v ils v ilts v ilex topr guaranteed range during high speed mode (1/2 dividing clock) operation guaranteed range during low speed mode (1/16 dividing clock) operation guaranteed data hold operation range during stop * 1 * 2 cmos schmitt input * 3 and pe0/int0 pins cmos schmitt input * 4 ttl schmitt input * 5 , * 8 extal pin * 6 , * 8 extal pin * 6 , * 7 * 2 , * 8 * 2 , * 7 cmos schmitt input * 3 , * 4 and pe0/int0 pins ttl schmitt input * 5 , * 8 extal pin * 6 , * 8 extal pin * 6 , * 7 v dd * 1 av dd and v dd should be set to a same voltage. * 2 normal input port (each pin of pc, pd, pf0 to pf3, pi pj, and pk), mp pin. * 3 each pin of sck0, rst, pe1/ec/int2, pi1/po, pi4/int1, pi5/sck1 and pi7/si1. * 4 each pin of cs0, si0, and pg (for pg and pg5, when cmos schmitt input is selected.) * 5 each pin of pg4 and pg5 (when ttl schmitt input is selected with mask option) * 6 it specifies only when the external clock is input. * 7 in case of 3.0 to 3.6v supply voltage (v dd ). * 8 in case of 4.5 to 5.5v supply voltage (v dd ). recommended operating conditions (vss = 0v)
?15 cxp87452/87460 v dd = 4.5v, i oh = ?.5ma v dd = 4.5v, i oh = ?.2ma v dd = 4.5v, i ol = 1.8ma v dd = 4.5v, i ol = 3.6ma v dd = 4.5v, i ol = 12.0ma v dd = 5.5v, v ih = 5.5v v dd = 5.5v, v il = 0.4v v dd = 5.5v, v il = 0.4v high level output voltage 4.0 3.5 0.5 ?.5 ?.5 v v v v v ? ? ? ? pd, ph pa to pe, pf4 to pf7, ph (v ol only) pi1 to pi7, pj, so, sck, rst * 1 (v ol only) extal rst * 2 item symbol pin condition min. other than v dd , vss, av dd , and avss pins clock 1mhz 0v other than the measured pins v dd i dd1 i iz i dds1 i dds3 c in v oh v ol i ihe i ile i ilr low level output voltage input current typ. 0.4 0.6 1.5 40 ?0 ?00 ?0 max. unit dc characteristics supply voltage (v dd ) 4.5 to 5.5v (ta = ?0 to +75?, vss = 0v) * 1 rst pin specifies only when the power on reset circuit has been selected with mask option. * 2 rst pin specifies the input current when the pull-up resistor is selected, and specifies leakage current when non-resistance is selected. * 3 when entire output pins are open. * 4 when setting upper 2 bits (cpu clock selection) of clock control register clc (address: 00fe h ) to "00" and operating in high speed mode (1/2 dividing clock). v dd = 5v 0.5v * 4 sleep mode v dd = 5v 0.5v v dd = 5.5v supply current * 3 input capacity v dd =5.5v, v i = 0, 5.5v crystal oscillation (c 1 = c 2 = 15pf) of 16mhz stop mode i/o leakage current pa to pk, mp, an0 to an3, cs, si, so, sck, rst * 2 31 2.0 10 50 8.0 10 20 ma ma ? pf electrical characteristics
?16 cxp87452/87460 v dd = 3.0v, i oh = ?.15ma v dd = 3.0v, i oh = ?.5ma v dd = 3.0v, i ol = 1.2ma v dd = 3.0v, i ol = 1.6ma v dd = 3.0v, i ol = 5.0ma v dd = 3.6v, v ih = 3.6v v dd = 3.6v, v il = 0.3v v dd = 3.6v, v il =0.3v high level output voltage 2.7 2.3 0.3 ?.3 ?.9 v v v v v ? ? ? ? pd, ph extal rst * 2 item symbol pin condition min. clock 1mhz 0v other than the measured pins v dd i dd2 i iz i dds2 i dds3 c in v oh v ol i ihe i ile i ilr low level output voltage input current typ. 0.3 0.5 1.0 20 ?0 ?00 ?0 max. unit supply voltage (v dd ) 3.0 to 3.6v (ta = ?0 to +75?, vss = 0v) * 1 rst pin specifies only where the power on reset circuit has been selected with mask option. * 2 rst pin specifies the input current when the pull-up resistor is selected, and specifies leakage current when non-resistance is selected. * 3 when entire output pins are open. * 4 when setting upper 2 bits (cpu clock selection) of clock control register clc (address: 00fe h ) to "00" and operating in high speed mode (1/2 dividing clock). v dd = 3.3v 0.3v * 4 sleep mode v dd = 3.3v 0.3v v dd = 5.5v supply current * 3 input capacity v dd = 5.5v, v i = 0, 5.5v crystal oscillation (c 1 = c 2 = 15pf) of 12mhz stop mode i/o leakage current pa to pk, mp, an0 to an3, cs, si, so, sck, rst * 2 15 0.8 10 30 2.5 10 20 ma ma ? pf pa to pe, pf4 to pf7, ph (v ol only) pi1 to pi7, pj, so, sck, rst * 1 (v ol only) other than v dd , vss, av dd , and avss pins
?17 cxp87452/87460 * t sys indicates three values according to the contents of the clock control register (address; 00fe h ) upper 2 bits (cpu clock selection). t sys [ns] = 2000/fc (upper 2 bits = "00"), 4000/fc (upper 2 bits = "01"), 16000/fc (upper 2 bits = "11") xtal t xh t xl t cf t cr 0.4v v dd ?0.4v 1/fc extal aaaa a aa a aaaa aaaa a aa a aaaa crystal oscillation ceramic oscillation extal xtal external clock extal xtal 74hc04 c 1 c 2 ac characteristics (1) clock timing system clock frequency system clock input pulse width system clock input rising and falling times event count clock input pulse width event count clock input rising and falling times f c t xl , t xh t cr , t cf t el , t eh t er , t ef xtal extal xtal extal xtal extal pe1/ec pe1/ec mhz ns ns ns ms item symbol pin condition unit fig. 1, fig. 2 fig. 1, fig. 2 (external clock drive) fig. 1, fig. 2 (external clock drive) fig. 3 fig. 3 min. 1 1 28 37.5 t sys 4 * max. 16 12 200 20 (ta = ?0 to +75?, v dd = 3.0 to 5.5v, vss = 0v) fig. 1. clock timing v dd = 4.5 to 5.5v v dd = 4.5 to 5.5v fig. 2. clock applied condition ec t eh t el t ef t er 0.2v dd 0.8v dd fig. 3. event count clock timing
?18 cxp87452/87460 input mode output mode input mode output mode sck input mode sck output mode sck input mode sck output mode sck input mode sck output mode chip select transfer mode (sck = output mode) chip select transfer mode (sck = output mode) chip select transfer mode chip select transfer mode chip select transfer mode note 1) t sys indicates three values according to the contents of the clock control register (address; 00fe h ) upper 2 bits (cpu clock selection). t sys [ns] = 2000/fc (upper 2 bits = "00"), 4000/fc (upper 2 bits = "01"), 16000/fc (upper 2 bits = "11") note 2) cs, sck, si and so means each pin of cs ? cs0, sck ? sck0, si ? si0, and so ? so0 respectively. note 3) the load of sck output mode and so output delay time is 50pf + 1ttl. (2) serial transfer (ch0) (ta = ?0 to +75?, v dd = 4.5 to 5.5v, vss = 0v) item cs ? sck delay time cs -? sck floating delay time cs ? so delay time cs ? so floating delay time cs high level width sck cycle time sck high and low level widths si input setup time (against sck - ) si input hold time 0 (against sck - ) sck ? so delay time t dcsk t dcskf t dcso t dcsof t whcs t kcy t kh t kl t sik t ksi t kso sck0 sck0 so0 so0 cs0 sck0 sck0 si0 si0 so0 ns ns ns ns ns symbol pin min. t sys + 200 t sys + 200 t sys + 200 t sys + 200 t sys + 200 2 t sys + 200 8000/fc t sys + 100 8000/fc ?100 t sys + 100 200 2 t sys + 100 100 ns ns ns ns ns ns ns ns ns ns 2 t sys + 200 100 max. unit condition
?19 cxp87452/87460 input mode output mode input mode output mode sck input mode sck output mode sck input mode sck output mode sck input mode sck output mode chip select transfer mode (sck = output mode) chip select transfer mode (sck = output mode) chip select transfer mode chip select transfer mode chip select transfer mode note 1) t sys indicates three values according to the contents of the clock control register (address; 00fe h ) upper 2 bits (cpu clock selection). t sys [ns] = 2000/fc (upper 2 bits = "00"), 4000/fc (upper 2 bits = "01"), 16000/fc (upper 2 bits = "11") note 2) cs, sck, si and so means each pin of cs ? cs0, sck ? sck0, si ? si0, and so ? so0 respectively. note 3) the load of sck output mode and so output delay time is 50pf. serial transfer (ch0) (ta = ?0 to +75?, v dd = 3.0 to 3.6v, vss = 0v) item cs ? sck delay time cs -? sck floating delay time cs ? so delay time cs ? so floating delay time cs high level width sck cycle time sck high and low level widths si input setup time (against sck - ) si input hold time (against sck - ) sck ? so delay time t dcsk t dcskf t dcso t dcsof t whcs t kcy t kh t kl t sik t ksi t kso sck0 sck0 so0 so0 cs0 sck0 sck0 si0 si0 so0 ns ns ns ns ns symbol pin min. t sys + 250 t sys + 200 t sys + 250 t sys + 200 t sys + 200 2 t sys + 200 16000/fc t sys + 100 8000/fc ?150 t sys + 100 200 2 t sys + 100 100 ns ns ns ns ns ns ns ns ns ns 2 t sys + 250 125 max. unit condition
?20 cxp87452/87460 fig. 4. serial transfer timing (ch0) cs0 sck0 0.2v dd 0.8v dd t whcs t dcsk t dcskf 0.8v dd 0.2v dd 0.8v dd t kcy t kl t kh 0.8v dd 0.2v dd si0 t sik t ksi input data t dcso t kso t dcsof output data 0.8v dd 0.2v dd so0
?21 cxp87452/87460 serial transfer (ch1) (sio mode) (ta = ?0 to +75?, v dd = 4.5 to 5.5v, vss = 0v) item symbol pin min. max. unit condition sck1 cycle time sck1 high and low level widths si1 input setup time (against sck1 - ) si1 input hold time (against sck1 - ) sck1 ? so1 delay time t kcy t kh t kl t sik t ksi t kso sck1 sck1 si1 si1 so1 input mode output mode input mode output mode sck1 input mode sck1 output mode sck1 input mode sck1 output mode sck1 input mode sck1 output mode 2 t sys + 200 16000/fc t sys + 100 8000/fc ?100 100 200 t sys + 200 100 t sys + 200 100 ns ns ns ns ns ns ns ns ns ns note 1) t sys indicates three values according to the contents of the clock control register (address; 00fe h ) upper 2 bits (cpu clock selection). t sys [ns] = 2000/fc (upper 2 bits = "00"), 4000/fc (upper 2 bits = "01"), 16000/fc (upper 2 bits = "11") note 2) the load of sck1 output mode and so1 output delay time is 50pf + 1ttl. serial transfer (ch1) (sio mode) (ta = ?0 to +75?, v dd = 3.0 to 3.6v, vss = 0v) item symbol pin min. max. unit condition sck1 cycle time sck1 high and low level widths si1 input setup time (against sck1 - ) si1 input hold time (against sck1 - ) sck1 ? so1 delay time t kcy t kh t kl t sik t ksi t kso sck1 sck1 si1 si1 so1 input mode output mode input mode output mode sck1 input mode sck1 output mode sck1 input mode sck1 output mode sck1 input mode sck1 output mode 2 t sys + 200 16000/fc t sys + 100 8000/fc ?150 100 200 t sys + 200 100 t sys + 250 125 ns ns ns ns ns ns ns ns ns ns note 1) t sys indicates three values according to the contents of the clock control register (address; 00fe h ) upper 2 bits (cpu clock selection). t sys [ns] = 2000/fc (upper 2 bits = "00"), 4000/fc (upper 2 bits = "01"), 16000/fc (upper 2 bits = "11") note 2) the load of sck1 output mode and so1 output delay time is 50pf.
?22 cxp87452/87460 fig. 5. serial transfer ch1 timing (sio mode) sck1 si1 so1 t kcy t kl t kh 0.2v dd 0.8v dd t sik t ksi t kso input data output data 0.2v dd 0.8v dd 0.2v dd 0.8v dd
?23 cxp87452/87460 so1 cycle time si1 data setup time si1 data hold time t lcy t lsu t lhd so1 si1 si1 si1 note 1) 2 2 104 s ? ? item symbol pin condition min. typ. max. unit serial transfer (ch1) (special mode) (ta = ?0 to +75?, v dd = 4.5 to 5.5v, vss = 0v) note 1) t lcy specifies only serial mode register (ch1) (siom1: address 01fa h ) lower 2 bits (so1 clock selection) has been set at 104s. note 2) the load of so1 pin is 50pf + 1ttl. so1 cycle time si1 data setup time si1 data hold time t lcy t lsu t lhd so1 si1 si1 si1 note 1) 2 2 104 s ? ? item symbol pin condition min. typ. max. unit serial transfer (ch1) (special mode) (ta = ?0 to +75?, v dd = 3.0 to 3.6v, vss = 0v) note 1) t lcy specifies only serial mode register (ch1) (siom1: address 01fa h ) lower 2 bits (so1 clock selection) has been set at 104s. note 2) the load of so1 pin is 50pf. fig. 6. serial transfer ch1 timing (special mode) so1 si1 t lcy start bit output data bit t lcy 0.5v dd 0.8v dd 0.2v dd t lcy/2 t lsu t lhd input data bit
?24 cxp87452/87460 fig. 7. definitions of a/d converter terms conversion time sampling time reference input voltage analog input voltage t conv t samp v ref v ian av ref an0 to an11 i ref only for a/d converter operation ta = 25? v dd = av dd = av ref = 5.0v v ss = av ss = 0v operating mode av ref = 4.0 to 5.5v v dd = av dd = 4.5 to 5.5v sleep mode stop mode linearity error absolute error resolution av ref current av ref ? ? v v av dd av ref 1.0 ma 10 ? 0.6 160/f adc 12/f adc av dd ?0.5 0 item symbol pin condition min. typ. max. unit bits (3) a/d converter characteristics (ta = ?0 to +75?, v dd = av dd = 4.5 to 5.5v, av ref = 4.0 to av dd , vss = av ss = 0v) 8 ? ? lsb lsb analog input linearity error v ft v zt 00 h 01 h fe h ff h digital conversion value * the value of f adc is as follows by selecting adc operation clock (msc: address 01ff h bit 0). when ps2 is selected, f adc = fc/2 when ps1 is selected, f adc = fc conversion time sampling time reference input voltage analog input voltage t conv t samp v ref v ian av ref an0 to an11 i ref only for a/d converter operation ta = 25? v dd = av dd = av ref = 3.3v v ss = av ss = 0v operating mode av ref = 2.7 to 3.6v sleep mode stop mode linearity error absolute error resolution av ref current av ref ? ? v v av dd av ref 0.7 ma 10 ? 0.4 160/f adc 12/f adc av dd ?0.3 0 item symbol pin condition min. typ. max. unit bits (ta = ?0 to +75?, v dd = av dd = 3.0 to 3.6v, av ref = 2.7 to av dd , vss = av ss = 0v) 8 ? ? lsb lsb a/d converter characteristics v dd = av dd = 3.0 to 3.6v
?25 cxp87452/87460 external interruption high and low level widths reset input low level width int0 int1 int2 pj0 to pj7 rst 1 32/fc ? ? item symbol pin condition min. max. unit t ih t il t rsl (4) interruption, reset input (ta = ?0 to +75?, v dd = 3.0 to 5.5v, vss = 0v) 0.2v dd 0.8v dd t ih t il int0 int1 int2 pj0 to pj7 (during standby release input) (falling edge) fig. 8. interruption input timing t rsl 0.2v dd rst fig. 9. reset input timing power supply rising edge power supply cut-off time t r t off v dd power on reset repetitive power on reset 0.05 1 30 ms ms item symbol pin condition min. max. unit (5) power on reset power on reset * (ta = ?0 to +75?, v dd = 3.0 to 5.5v, vss = 0v) 0.2v 0.2v 3.0v v dd t r t off the power supply should rise smoothly. fig. 10. power on reset * specifies only when power on reset function is selected.
?26 cxp87452/87460 external clock input frequency external clock input pulse width external clock input rising and falling times prescaler output delay time (against pck - ) prescaler output rising and falling times f pck t wh , t wl t r , t f t plh t phl t tlh t thl pck pck pck po po external clock input pck t r = t f = 6ns external clock input pck t r = t f = 6ns 33 80 60 50 20 12 200 130 100 100 40 mhz ns ns ns ns ns ns item symbol pin condition min. typ. max. unit (6) general purpose prescaler note) the load of po pin is 50pf. (ta = ?0 to +75?, v dd = 4.5 to 5.5v, vss = 0v) external clock input frequency external clock input pulse width external clock input rising and falling times prescaler output delay time (against pck - ) prescaler output rising and falling times f pck t wh , t wl t r , t f t plh t phl t tlh t thl pck pck pck po po external clock input pck t r = t f = 6ns external clock input pck t r = t f = 6ns 33 130 90 100 30 12 200 220 150 280 70 mhz ns ns ns ns ns ns item symbol pin condition min. typ. max. unit general purpose prescaler note) the load of po pin is 50pf. (ta = ?0 to +75?, v dd = 3.0 to 3.6v, vss = 0v) 1/f pck t f t wh 0.8v dd t r t wl 0.5v dd 0.2v dd t plh 0.8v dd 0.5v dd 0.2v dd t tlh t thl t phl pck po fig. 11. general purpose prescaler timing
?27 cxp87452/87460 (7) others (ta = ?0 to +75?, v dd = 3.0 to 5.5v, vss = 0v) item cfg input high and low level widths dfg input high and low level widths dpg minimum pulse width dpg minimum removal time pbctl input high and low level widths exi input high and low level widths pmi input high and low level widths pmsk input high and low level widths t cfh t cfl t dfh t dfl t dpw t rem t cth t ctl t eih t eil t pih t pil t psh t psl cfg dfg dpg dpg pbctl exi0 exi1 pmi pmsk ns ns ns ns ns ns ns ns symbol pin min. t frc 24 + 200 t frc 8 + 200 50 50 t frc 8 + t sys + 200 t frc 8 + t sys + 200 t sys + 200 t sys + 200 max. unit t sys = 2000/fc t sys = 2000/fc condition note 1) t sys indicates three values according to the contents of the clock control register (address; 00fe h ) upper 2 bits (cpu clock selection). t sys [ns] = 2000/fc (upper 2 bits = "00"), 4000/fc (upper 2 bits = "01"), 16000/fc (upper 2 bits = "11") note 2) the value of t frc is as follows by selecting frc clock (frcs: 01ee h bit 7) when ps0 is selected, t frc = 1000/fc (ns) when ps1 is selected, t frc = 2000/fc (ns)
?28 cxp87452/87460 0.8v dd cfg t cfh t cfl 0.2v dd 0.8v dd dfg t dfh t dfl 0.2v dd 0.8v dd pbctl t cth t ctl 0.2v dd 0.8v dd exi0 exi0 t eih t eil 0.2v dd 0.8v dd t rem t dpw t rem dpg fig. 12. other timings
?29 cxp87452/87460 0.8v dd pmi t pih t pil 0.2v dd 0.8v dd pmsk t psh t psl 0.2v dd
?30 cxp87452/87460 supplement fig. 13. recommended oscillation circuit a aa a aaaa extal xtal c 1 c 2 rd main clock * in pg4/sync0/pmi pin and pg5/sync1 pin, the input circuit format can be selected every pin. however, ttl schmitt can not be selected when the supply voltage (v dd ) ranges from 3.5v to 5.5v. reset pin pull-up resistor power on reset circuit genaral purpose prescaler oscillation circuit input circuit format * non-existent non-existent non-existent cmos schmitt item content existent existent existent ttl schmitt manufacturer model fc (mhz) c 1 (pf) c 2 (pf) rd ( ) circuit example river eletec co., ltd. hc-49/u03 kinseki ltd. hc-49/u (-s) 8.00 10.00 12.00 16.00 8.00 10.00 12.00 16.00 10 5 22 (15) 15 12 10 5 22 (15) 15 12 0 0 (i) (i) mask option table
?31 cxp87452/87460 i dd vs. fc (v dd = 3.3v, ta = 25?, typical) 20 510 16 0 30 10 1/2 dividing mode 1/4 dividing mode 1/16 dividing mode sleep mode i dd vs. fc (v dd = 5v, ta = 25?, typical) 20 fc ?system clock [mhz] 510 16 0 30 10 1/2 dividing mode 1/4 dividing mode 1/16 dividing mode sleep mode i dd vs. v dd (fc = 12mhz, ta = 25?, typical) 20.0 10.0 5.0 1.0 0.5 0.1 (100a) 0.05 (50a) 0.01 (10a) 34567 1/2 dividing mode 1/4 dividing mode 1/16 dividing mode sleep mode i dd vs. v dd (fc = 16mhz, ta = 25?, typical) 20.0 10.0 5.0 1.0 0.5 0.1 (100a) 0.05 (50a) 0.01 (10a) v dd ?supply voltage [v] 34 56 i dd ?supply current [ma] 7 1/2 dividing mode 1/4 dividing mode 1/16 dividing mode sleep mode 15 15 i dd ?supply current [ma] i dd ?supply current [ma] i dd ?supply current [ma] fc ?system clock [mhz] v dd ?supply voltage [v] characteristics curve
?32 cxp87452/87460 package outline unit: mm sony code eiaj code jedec code package material lead treatment lead material package weight epoxy resin solder plating copper / 42 alloy package structure 23.9 0.4 qfp-100p-l01 detail a m 100pin qfp (plastic) 20.0 ?0.1 + 0.4 0?to 15 0.15 ?0.05 + 0.1 15.8 0.4 17.9 0.4 14.0 ?0.01 + 0.4 2.75 ?0.15 + 0.35 a 0.65 0.12 0.15 0.8 0.2 (16.3) * qfp100-p-1420-a 1.4g sony code eiaj code jedec code package material lead treatment lead material package weight epoxy/phenol resin solder plating 42 alloy package structure detail a lqfp-100p-l01 * qfp100-p-1414-a 100pin lqfp (plastic) 16.0 0.2 * 14.0 0.1 75 51 50 26 25 1 76 0.5 0.08 0.18 ?0.03 + 0.08 (0.22) a 1.5 ?0.1 + 0.2 0.127 ?0.02 + 0.05 0.5 0.2 (15.0) 0?to 10 0.1 0.1 0.5 0.2 100 0.1 note: dimension * ?does not include mold protrusion.

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